PIC17C75X
FIGURE 15-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h, Unbanked INTSTA
PEIF
T0CKIF
BCLIF
T0IF
INTF
—
PEIE
T0CKIE
CA3IF
T0IE
INTE
0000 0000
000- 0010
000- 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
000- 0010
000- 0000
uuuu uuuu
0000 0000
0000 0000
10h, Bank 4
11h, Bank 4
14h, Bank 6
11h, Bank 6
13h, Bank 6
Legend:
PIR2
SSPIF
ADIF
CA4IF
TX2IF
RC2IF
PIE2
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1 WCOL SSPOV
SSPSTAT SMP CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 133
MICROCHIP [ MICROCHIP ]
