PIC16F913/914/916/917/946
The PWM output (Figure 15-2) has a time base
(period) and a time that the output stays high (duty
cycle).
15.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
FIGURE 15-4:
CCP PWM OUTPUT
• PR2
Period
• T2CON
• CCPRxL
• CCPxCON
Pulse Width
TMR2 = PR2
TMR2 = CCPRxL:CCPxCON<5:4>
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCPx pin. Since the CCPx pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCPx pin output driver.
TMR2 = 0
Note:
Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Figure 15-3 shows a simplified block diagram of PWM
operation.
Figure 15-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.3.7
“Setup for PWM Operation”.
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers
CCPRxL
CCPRxH(2) (Slave)
CCPx
R
S
Q
Comparator
(1)
TMR2
TRIS
Comparator
PR2
Clear Timer2,
toggle CCPx pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
2: In PWM mode, CCPRxH is a read-only register.
© 2007 Microchip Technology Inc.
DS41250F-page 215
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