PIC16F913/914/916/917/946
15.1.2
TIMER1 MODE SELECTION
15.1 Capture Mode
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
In Capture mode, CCPRxH:CCPRxL captures the
16-bit value of the TMR1 register when an event occurs
on pin CCPx. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
15.1.3
SOFTWARE INTERRUPT
• Every falling edge
• Every rising edge
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in operating mode.
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value (see Figure 15-1).
15.1.4
CCP PRESCALER
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
15.1.1
CCPx PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler (see Example 15-1).
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 15-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSELCCP1CON
;Set Bank bits to point
;to CCP1CON
;Turn CCP module off
Set Flag bit CCPxIF
(PIRx register)
Prescaler
÷ 1, 4, 16
CLRF
CCP1CON
MOVLW
NEW_CAPT_PS;Load the W reg with
; the new prescaler
CCPx
pin
CCPRxH
CCPRxL
; move value and CCP ON
Capture
Enable
MOVWF
CCP1CON
;Load CCP1CON with this
; value
and
Edge Detect
TMR1H
TMR1L
CCPxCON<3:0>
System Clock (FOSC)
© 2007 Microchip Technology Inc.
DS41250F-page 213
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