PIC16F913/914/916/917/946
FIGURE 14-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX-1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON
TABLE 14-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION
Value on all
other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
LCDCON
LCDSE1
PIE1
GIE
LCDEN
SE15
EEIE
PEIE
SLPEN
SE14
ADIE
ADIF
T0IE
INTE
RBIE
CS1
T0IF
CS0
INTF
LMUX1
SE9
RBIF
0000 000x 0000 000x
WERR VLCDEN
LMUX0 0001 0011 0001 0011
SE8 0000 0000 0000 0000
SE13
RCIE
RCIF
SREN
SE12
TXIE
SE11
SE10
SSPIE
SSPIF
ADDEN
CCP1IE TMR2IF TMR1IF 0000 0000 0000 0000
0000 0000 0000 0000
0000 000x
xxxx xxxx uuuu uuuu
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
R/W UA BF 0000 0000 0000 0000
PIR1
EEIF
TXIF
CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
RCSTA
SPEN
RX9
CREN
0000 000x
SSPBUF
SSPCON
SSPSTAT
TRISC
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV SSPEN
CKP
P
(1)
(1)
SMP
CKE
D/A
S
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend:
– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the SSP module.
Note 1: Maintain these bits clear.
© 2007 Microchip Technology Inc.
DS41250F-page 209