PIC16F882/883/884/886/887
3.6.1
RD<4:0>
3.6.3
RD6/P1C(1)
Figure 3-19 shows the diagram for these pins. These
pins are configured to function as general purpose
I/O’s.
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a PWM output
Note:
RD<4:0> is available on PIC16F884/887
only.
Note 1: RD6/P1C is available on PIC16F884/887
only. See RB1/AN10/P1C/C12IN3- for
this function on PIC16F882/883/886.
FIGURE 3-19:
BLOCK DIAGRAM OF
RD<4:0>
3.6.4
RD7/P1D(1)
Data Bus
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
VDD
D
Q
• a general purpose I/O
• a PWM output
WR
PORTD
CK
Q
Note 1: RD7/P1D is available on PIC16F884/887
only. See RB4/AN11/P1D for this function
on PIC16F882/883/886.
I/O Pin
D
Q
Q
WR
TRISD
CK
VSS
FIGURE 3-20:
BLOCK DIAGRAM OF
RD<7:5>
RD
TRISD
Data Bus
D
PSTRCON
RD
PORTD
VDD
Q
Q
WR
CK
10
CCP1
PORTD
3.6.2
RD5/P1B(1)
0
I/O Pin
Figure 3-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
D
Q
Q
WR
TRISD
CK
• a general purpose I/O
• a PWM output
VSS
RD
TRISD
Note 1: RD5/P1B is available on PIC16F884/887
only. See RB2/AN8/P1B for this function
on PIC16F882/883/886.
RD
PORTD
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
PSTRCON
TRISD
RD7
—
RD6
—
RD5
—
RD4
RD3
STRD
RD2
STRC
RD1
STRB
RD0
STRA
xxxx xxxx
---0 0001
1111 1111
uuuu uuuu
---0 0001
1111 1111
STRSYNC
TRISD4
TRISD7
TRISD6
TRISD5
TRISD3
TRISD2
TRISD1
TRISD0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
DS41291D-page 58
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
