PIC16F882/883/884/886/887
3.7.1
RE0/AN5(1)
3.7.4
RE3/MCLR/VPP
This pin is configurable to function as one of the
following:
Figure 3-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a general purpose input
• an analog input for the ADC
• as Master Clear Reset with weak pull-up
Note 1: RE0/AN5 is available on PIC16F884/887
FIGURE 3-22:
BLOCK DIAGRAM OF RE3
only.
VDD
3.7.2
RE1/AN6(1)
MCLRE
Weak
This pin is configurable to function as one of the
following:
Data Bus
MCLRE
Reset
Input
Pin
• a general purpose I/O
• an analog input for the ADC
RD
TRISE
VSS
Note 1: RE1/AN6 is available on PIC16F884/887
MCLRE
VSS
RD
PORTE
only.
3.7.3
RE2/AN7(1)
This pin is configurable to function as one of the
following:
• a general purpose I/O
• an analog input for the ADC
Note 1: RE2/AN7 is available on PIC16F884/887
only.
FIGURE 3-21:
BLOCK DIAGRAM OF
RE<2:0>
Data Bus
VDD
D
Q
WR
PORTE
CK
Q
I/O Pin
D
Q
Q
WR
TRISE
CK
VSS
Analog(1)
Input Mode
RD
TRISE
RD
PORTE
To A/D Converter
Note 1: ANSEL determines Analog Input mode.
TABLE 3-5:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
POR, BOR
Value on
all other Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSEL
PORTE
TRISE
ANS7 ANS6 ANS5 ANS4
ANS3
RE3
ANS2
RE2
ANS1
RE1
ANS0
RE0
1111 1111
---- xxxx
---- 1111
1111 1111
---- uuuu
---- 1111
—
—
—
—
—
—
—
—
TRISE3 TRISE2 TRISE1 TRISE0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE
DS41291D-page 60
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
