PIC16F882/883/884/886/887
3.5.7
RC6/TX/CK
3.5.8
RC7/RX/DT
Figure 3-17 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 3-18 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an asynchronous serial output
• a synchronous clock I/O
• an asynchronous serial input
• a synchronous serial data I/O
FIGURE 3-17:
BLOCK DIAGRAM OF RC6
FIGURE 3-18:
BLOCK DIAGRAM OF RC7
SPEN
SYNC
SPEN
TXEN
Data Bus
SYNC
EUSART
VDD
EUSART
CK
Data Bus
D
CK
Q
Q
10
DT
10
EUSART
TX
WR
PORTC
0
VDD
0
D
Q
I/O Pin
10
WR
PORTC
CK
D
Q
Q
Q
01
WR
TRISC
CK
VSS
I/O Pin
D
Q
Q
RD
TRISC
WR
TRISC
CK
VSS
RD
PORTC
RD
TRISC
EUSART RX/DT
RD
PORTC
TABLE 3-3:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCP2CON
PORTC
P1M1
—
P1M0
—
DC1B1
DC2B1
RC5
DC1B0
DC2B0
RC4
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
0000 0000
--00 0000
xxxx xxxx
---0 0001
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
--00 0000
uuuu uuuu
---0 0001
0000 000x
0000 0000
0000 0000
1111 1111
RC7
—
RC6
—
RC3
RC2
STRC
FERR
SSPM2
RC1
STRB
OERR
SSPM1
RC0
STRA
RX9D
SSPM0
PSTRCON
RCSTA
—
STRSYNC
CREN
STRD
SPEN
RX9
SREN
SSPEN
ADDEN
SSPM3
SSPCON
T1CON
WCOL
SSPOV
CKP
T1GINV
TMR1GE
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TRISC
TRISC7
TRISC6
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
DS41291D-page 56
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
