PIC16F87/88
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. For more information, see Application Note,
AN607 “Power-up Trouble Shooting” (DS00607).
15.3 MCLR
PIC16F87/88 devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin, that exceed its specifica-
tion, can result in both MCLR and excessive current
beyond the device specification during the ESD event.
The circuit, as shown in Figure 15-2, is suggested.
15.5 Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC16F87/88 is a
counter that uses the INTRC oscillator as the clock
input. This yields a count of 72 ms. While the PWRT is
counting, the device is held in RESET.
Note:
For this reason, Microchip recommends
that the MCLR pin no longer be tied
directly to VDD.
The power-up time delay depends on the INTRC, and
will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The RA5/MCLR pin can be configured for MCLR
(default), or as an I/O pin (RA5). This is configured
through the MCLRE bit in Configuration Word 1.
The PWRT is enabled by clearing configuration bit
PWRTEN.
15.6 Oscillator Start-up Timer (OST)
FIGURE 15-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
VDD
D
R
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
SLEEP.
R1
MCLR
PIC16F87/88
C
15.7 Brown-out Reset (BOR)
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 µs), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer (if enabled) will keep the device in
RESET for TPWRT (parameter #33, about 72 ms). If
VDD should fall below VBOR during TPWRT, the Brown-
out Reset process will restart when VDD rises above
VBOR, with the Power-up Timer Reset. Unlike previous
PIC16 devices, the PWRT is no longer automatically
enabled when the Brown-out Reset circuit is enabled.
The PWRTEN and BOREN configuration bits are
independent of each other.
3: R1 = 1 kΩ to 10 kΩ will limit any current flow-
ing into MCLR from external capacitor C
(0.1 µF), in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
15.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to VDD, as
described in Section 15.3 “MCLR”. A maximum rise
time for VDD is specified. See Section 18.0 “Electrical
Characteristics” for details.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 133
MICROCHIP [ MICROCHIP ]
