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PIC16F688-I/ST 参数 Datasheet PDF下载

PIC16F688-I/ST图片预览
型号: PIC16F688-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 202 页 / 3832 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F688  
It is recommended, therefore, that only BCF, BSF,  
SWAPF and MOVWF instructions are used to alter the  
STATUS register, because these instructions do not  
affect any Status bits. For other instructions not affect-  
ing any Status bits (see Section 12.0 “Instruction Set  
Summary”).  
2.2.2.1  
STATUS Register  
The STATUS register, shown in Register 2-1, contains:  
• the arithmetic status of the ALU  
• the Reset status  
• the bank select bits for data memory (SRAM)  
The STATUS register can be the destination for any  
instruction, like any other register. If the STATUS  
register is the destination for an instruction that affects  
the Z, DC or C bits, then the write to these three bits is  
disabled. These bits are set or cleared according to the  
device logic. Furthermore, the TO and PD bits are not  
writable. Therefore, the result of an instruction with the  
STATUS register as destination may be different than  
intended.  
Note 1: Bits IRP and RP1 of the STATUS register  
are not used by the PIC16F688 and  
should be maintained as clear. Use of  
these bits is not recommended, since this  
may affect upward compatibility with  
future products.  
2: The C and DC bits operate as a Borrow  
and Digit Borrow out bit, respectively, in  
subtraction.  
For example, CLRF STATUSwill clear the upper three  
bits and set the Z bit. This leaves the STATUS register  
as ‘000u u1uu(where u= unchanged).  
REGISTER 2-1:  
STATUS: STATUS REGISTER  
R/W-0  
IRP  
R/W-0  
RP1  
R/W-0  
RP0  
R-1  
TO  
R-1  
PD  
R/W-x  
Z
R/W-x  
R/W-x  
(1)  
(1)  
DC  
C
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
IRP: Register Bank Select bit (used for indirect addressing)  
1= Bank 2, 3 (100h-1FFh)  
0= Bank 0, 1 (00h-FFh)  
bit 6-5  
RP<1:0>: Register Bank Select bits (used for direct addressing)  
00= Bank 0 (00h-7Fh)  
01= Bank 1 (80h-FFh)  
10= Bank 2 (100h-17Fh)  
11= Bank 3 (180h-1FFh)  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
TO: Time-out bit  
1= After power-up, CLRWDTinstruction or SLEEPinstruction  
0= A WDT time-out occurred  
PD: Power-down bit  
1= After power-up or by the CLRWDTinstruction  
0= By execution of the SLEEPinstruction  
Z: Zero bit  
1= The result of an arithmetic or logic operation is zero  
0= The result of an arithmetic or logic operation is not zero  
(1)  
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)  
1= A carry-out from the 4th low-order bit of the result occurred  
0= No carry-out from the 4th low-order bit of the result  
(1)  
(1)  
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)  
1= A carry-out from the Most Significant bit of the result occurred  
0= No carry-out from the Most Significant bit of the result occurred  
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.  
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  
© 2007 Microchip Technology Inc.  
DS41203D-page 13  
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