PIC16F688
TABLE 2-3:
PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2
Value on
POR/BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
INDF
TMR0
PCL
STATUS
FSR
PORTA
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s register
xxxx xxxx
20, 117
45, 117
19, 117
13, 117
20, 117
33, 117
xxxx xxxx
Program Counter’s (PC) Least Significant Byte
0000 0000
IRP
RP1
RP0
TO
PD
Z
DC
RA1
RC1
C
0001 1xxx
Indirect Data Memory Address Pointer
xxxx xxxx
—
—
—
RA5
RC5
RA4
RC4
RA3
RC3
RA2
RC2
RA0
RC0
--x0 x000
Unimplemented
—
—
—
42, 117
—
PORTC
—
--xx 0000
Unimplemented
Unimplemented
—
—
—
—
—
PCLATH
INTCON
—
—
—
Write Buffer for upper 5 bits of Program Counter
INTE RAIE T0IF INTF
---0 0000
19, 117
15, 117
—
GIE
PEIE
T0IE
RAIF(2)
0000 000x
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
© 2007 Microchip Technology Inc.
DS41203D-page 11
MICROCHIP [ MICROCHIP ]
