PIC16F688
TABLE 2-2:
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR/BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
—
20, 117
14, 117
19, 117
13, 117
20, 117
33, 117
—
OPTION_REG
PCL
RAPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
STATUS
FSR
PD
Z
DC
C
TRISA
—
—
—
TRISA5
TRISA4
TRISA3
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISC0
Unimplemented
TRISC
—
—
—
TRISC5
TRISC4
--11 1111
—
42, 117
—
Unimplemented
Unimplemented
—
—
—
PCLATH
INTCON
PIE1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
0000 000x
19, 117
15, 117
16, 117
—
GIE
EEIE
PEIE
ADIE
T0IE
RCIE
INTE
C2IE
RAIE
C1IE
T0IF
INTF
TXIE
RAIF(3)
OSFIE
TMR1IE 0000 0000
—
Unimplemented
—
PCON
OSCCON
OSCTUNE
ANSEL
—
—
—
—
ULPWUE SBOREN
—
—
POR
LTS
BOR
SCS
--01 --qq
-110 x000
---0 0000
1111 1111
—
18, 117
22, 118
26, 118
34, 118
—
IRCF2
—
IRCF1
—
IRCF0
TUN4
ANS4
OSTS
TUN3
ANS3
HTS
—
TUN2
ANS2
TUN1
ANS1
TUN0
ANS0
ANS7
ANS6
ANS5
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
WPUA(2)
—
—
—
WPUA5
IOCA5
WPUA4
IOCA4
—
WPUA2
IOCA2
WPUA1
IOCA1
WPUA0
IOCA0
--11 -111
--00 0000
35, 118
35, 118
78, 118
78, 118
63, 118
78, 118
78, 118
79, 118
77, 118
72, 118
71, 118
IOCA
—
—
—
—
IOCA3
EEDATH
EEADRH
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
—
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000
—
—
—
—
EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000
VREN
VRR
VR3
VR2
VR1
EEDAT1
EEADR1
WR
VR0
0-0- 0000
EEDAT7 EEDAT6
EEDAT5
EEDAT4
EEADR4
—
EEDAT3
EEADR3
WRERR
EEDAT2
EEADR2
WREN
EEDAT0 0000 0000
EEADR0 0000 0000
EEADR7 EEADR6 EEADR5
EEPGD
—
—
RD
x--- x000
---- ----
xxxx xxxx
-000 ----
EEPROM Control 2 Register (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
ADCS2 ADCS1 ADCS0 —
—
—
—
—
Legend:
Note 1:
– = Unimplemented locations read as ‘0’, u = unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
2:
3:
DS41203D-page 10
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
