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PIC16F688-I/ST 参数 Datasheet PDF下载

PIC16F688-I/ST图片预览
型号: PIC16F688-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 202 页 / 3832 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F688  
2.2.2.5  
PIR1 Register  
The PIR1 register contains the interrupt flag bits, as  
shown in Register 2-5.  
Note:  
Interrupt flag bits are set when an interrupt  
condition occurs, regardless of the state of  
its corresponding enable bit or the global  
enable bit, GIE bit of the INTCON register.  
User software should ensure the appropri-  
ate interrupt flag bits are clear prior to  
enabling an interrupt.  
REGISTER 2-5:  
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1  
R/W-0  
EEIF  
R/W-0  
ADIF  
R-0  
R/W-0  
C2IF  
R/W-0  
C1IF  
R/W-0  
OSFIF  
R-0  
R/W-0  
RCIF  
TXIF  
TMR1IF  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
EEIF: EEPROM Write Operation Interrupt Flag bit  
1= The write operation completed (must be cleared in software)  
0= The write operation has not completed or has not been started  
ADIF: A/D Converter Interrupt Flag bit  
1= A/D conversion complete (must be cleared in software)  
0= A/D conversion has not completed or has not been started  
RCIF: EUSART Receive Interrupt Flag bit  
1= The EUSART receive buffer is full (cleared by reading RCREG)  
0= The EUSART receive buffer is not full  
C2IF: Comparator C2 Interrupt Flag bit  
1= Comparator output (C2OUT bit) has changed (must be cleared in software)  
0= Comparator output (C2OUT bit) has not changed  
C1IF: Comparator C1 Interrupt Flag bit  
1= Comparator output (C1OUT bit) has changed (must be cleared in software)  
0= Comparator output (C1OUT bit) has not changed  
OSFIF: Oscillator Fail Interrupt Flag bit  
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)  
0= System clock operating  
TXIF: EUSART Transmit Interrupt Flag bit  
1= The EUSART transmit buffer is empty (cleared by writing to TXREG)  
0= The EUSART transmit buffer is full  
TMR1IF: Timer1 Overflow Interrupt Flag bit  
1= The TMR1 register overflowed (must be cleared in software)  
0= The TMR1 register did not overflow  
© 2007 Microchip Technology Inc.  
DS41203D-page 17  
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