PIC16F688
TABLE 2-1:
PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0
Value on
POR/BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s register
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--x0 x000
—
20, 117
45, 117
19, 117
TMR0
PCL
Program Counter’s (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
RA1
RC1
C
13, 117
20, 117
33, 117
Indirect Data Memory Address Pointer
PORTA
—
—
—
RA5
RC5
RA4
RC4
RA3
RC3
RA2
RC2
RA0
RC0
Unimplemented
—
42, 117
—
PORTC
—
—
—
--xx 0000
—
Unimplemented
Unimplemented
—
—
—
19, 117
PCLATH
INTCON
PIR1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
0000 000x
0000 0000
—
GIE
EEIF
PEIE
ADIF
T0IE
RCIF
INTE
C2IF
RAIE
C1IF
T0IF
INTF
TXIF
RAIF(2)
15, 117
17, 117
—
OSFIF
TMR1IF
—
Unimplemented
48, 117
48, 117
TMR1L
TMR1H
T1CON
BAUDCTL
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
WDTCON
CMCON0
CMCON1
—
Holding Register for the Least Significant Byte of the 16-bit TMR1
Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
xxxx xxxx
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000
51, 117
94, 117
95, 117
95, 117
87, 117
87, 117
92, 117
93, 117
124, 117
61, 117
62, 117
—
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
USART Baud Rate High Generator
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
CSRC
SPEN
—
TX9
RX9
—
TXEN
SREN
—
SYNC
CREN
WDTPS3
C1INV
—
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000
C2OUT
—
C1OUT
—
C2INV
—
CIS
—
CM2
—
CM1
CM0
0000 0000
T1GSS
C2SYNC ---- --10
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
72, 117
71, 117
ADRESH
ADCON0
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADFM VCFG CHS2 CHS1 CHS0 GO/DONE
xxxx xxxx
—
ADON
00-0 0000
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
© 2007 Microchip Technology Inc.
DS41203D-page 9
MICROCHIP [ MICROCHIP ]
