PIC16F688
As the impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
8.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error is
used (1024 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
Figure 8-4.
impedance for analog sources is 10 kΩ.
The
maximum
recommended
To calculate the minimum acquisition time, TACQ, see
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
EQUATION 8-1:
ACQUISITION TIME
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2 µs + TC + [(Temperature -25°C)(0.05 µs/°C)]
TC = CHOLD (RIC + RSS + RS) In(1/2047)
= -120 pF(1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885)
= 16.47 µs
TACQ = 2 µs + 16.47 µs + [(50°C -25°C)(0.05 µs/°C)]
= 19.72 µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
FIGURE 8-4:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
= DAC capacitance
= 120 pF
CPIN
5 pF
VA
ILEAKAGE
± 500 nA
VT = 0.6V
VSS
6V
5V
VDD 4V
3V
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
2V
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
SS
CHOLD
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
(kΩ)
DS41203B-page 68
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
