PIC16F688
8.1.7
CONFIGURING THE A/D
EXAMPLE 8-1:
A/D CONVERSION
;This code block configures the A/D
;for polling, Vdd reference, R/C clock
;and RA0 input.
;
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
;Conversion start & wait for complete
;polling code included.
;
To determine sample time, see Section 14.0 “Electrical
Specifications”. After this sample time has elapsed, the
A/D conversion can be started.
BSF
STATUS,RP0
;Bank 1
MOVLW B’01110000’
MOVWF ADCON1
;A/D RC clock
These steps should be followed for an A/D conversion:
BSF
BSF
BCF
TRISA,0
ANSEL,0
STATUS,RP0
;Set RA0 to input
;Set RA0 to analog
;Bank 0
1. Configure the A/D module:
• Configure analog/digital I/O (ANSEL)
• Configure voltage reference (ADCON0)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON1)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit (PIR1<6>)
MOVLW B’10000001’
MOVWF ADCON0
CALL
BSF
BTFSC ADCON0,GO
GOTO
MOVF
MOVWF RESULTHI
BSF
MOVF
MOVWF RESULTLO
;Right, Vdd Vref, AN0
SampleTime
ADCON0,GO
;Wait min sample time
;Start conversion
;Is conversion done?
;No, test again
$-1
ADRESH,W
;Read upper 2 bits
• Set ADIE bit (PIE1<6>)
STATUS,RP0
ADRESL,W
;Bank 1
;Read lower 8 bits
• Set PEIE and GIE bits (INTCON<7:6>)
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0<0>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
• Waiting for the A/D interrupt
6. Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 67
MICROCHIP [ MICROCHIP ]
