PIC16F688
FIGURE 11-8:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(2)
(5)
Interrupt Latency
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
0004h
PC + 1
PC + 1
—
0005h
PC
Instruction
Fetched
Inst (PC)
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC - 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 14.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 11-6: SUMMARY OF INTERRUPT REGISTERS
Value on
all other
Resets
Value on
POR, BOD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh INTCON
GIE
EEIF
EEIE
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
C2IF
C2IE
RAIE
C1IF
C1IE
T0IF
INTF
TXIF
TXIE
RAIF
0000 0000 0000 0000
0Ch
PIR1
PIE1
OSFIF
OSFIE
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
8Ch
Legend:
x= unknown, u= unchanged, — = unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by the interrupt module.
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 111
MICROCHIP [ MICROCHIP ]
