PIC16F688
11.5.1
RA2/INT INTERRUPT
11.5.2
TMR0 INTERRUPT
External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit (OPTION<6>) is set, or
falling, if the INTEDG bit is clear. When a valid edge
appears on the RA2/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The RA2/INT
interrupt can wake-up the processor from Sleep if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up
(0004h). See Section 11.8 “Power-Down Mode
(Sleep)” for details on Sleep and Figure 11-10 for
timing of wake-up from Sleep through RA2/INT
interrupt.
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled
by
setting/clearing
T0IE
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
11.5.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Note:
The ANSEL (91h) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
FIGURE 11-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
Wake-up (If in Sleep mode)
Interrupt to CPU
T0IF
T0IE
TXIF
TXIE
INTF
INTE
RAIF
TMR1IF
TMR1IE
RAIE
C1IF
C1IE
PEIE
GIE
C2IF
C2IE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
RCIF
RCIE
DS41203B-page 110
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
