PIC16F688
REGISTER 11-3: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
bit 0
bit 7
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’
WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset value)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
bit 0
SWDTEN: Software Enable or Disable the Watchdog Timer(1)
1= WDT is turned on
0= WDT is turned off (Reset value)
Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this
control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with
this control bit.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
TABLE 11-8: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
WDTCON
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18h
81h
—
—
—
WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN
RAPU INTEDG
CPD CP
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of all Configuration Word register bits.
T0CS
T0SE
PSA
PS2
PS1
PS0
2007h(1) CONFIG
MCLRE PWRTE
WDTE
FOSC2 FOSC1 FOSC0
DS41203B-page 114
Preliminary
2004 Microchip Technology Inc.