PIC16F688
A new prescaler has been added to the path between
the INTRC and the multiplexers used to select the path
for the WDT. This prescaler is 16 bits and can be
programmed to divide the INTRC by 32 to 65536,
giving the WDT a nominal range of 1 ms to 268s.
11.7 Watchdog Timer (WDT)
For PIC16F688, the WDT has been modified from
previous 16F devices. The new WDT is code and
functionally compatible with previous 16F WDT
modules and adds a 16-bit prescaler to the WDT. This
allows the user to have a scaler value for the WDT and
TMR0 at the same time. In addition, the WDT time-out
value can be extended to 268 seconds. WDT is cleared
under certain conditions described in Table 11-7.
11.7.2
WDT CONTROL
The WDTE bit is located in the Configuration Word
register. When set, the WDT runs continuously.
When the WDTE bit in the Configuration Word register
is set, the SWDTEN bit (WDTCON<0>) has no effect.
If WDTE is clear, then the SWDTEN bit can be used to
enable and disable the WDT. Setting the bit will enable
it and clearing the bit will disable it.
11.7.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz
LFINTOSC. The LTS bit does not reflect that the
LFINTOSC is enabled.
The PSA and PS<2:0> bits (OPTION_REG) have the
same function as in previous versions of the 16F family
of microcontrollers. See Section 5.0 “Timer0 Module”
for more information.
The value of WDTCON is ‘---0 1000’on all Resets.
This gives a nominal time base of 16 ms, which is
compatible with the time base generated with previous
16F microcontroller versions.
Note:
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
FIGURE 11-9:
WATCHDOG TIMER BLOCK DIAGRAM
0
1
From TMR0 Clock Source
Prescaler(1)
16-bit WDT Prescaler
8
PSA
PS<2:0>
To TMR0
31 kHz
LFINTOSC Clock
WDTPS<3:0>
1
0
PSA
WDTE from Configuration Word Register
SWDTEN from WDTCON
WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.
TABLE 11-7: WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDTCommand
Oscillator Fail Detected
Cleared
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 113
MICROCHIP [ MICROCHIP ]
