PIC16F7X7
9.5.1
CCP PIN CONFIGURATION
9.5.4
SPECIAL EVENT TRIGGER
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note:
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1<0>).
9.5.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.5.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCP1IF or CCP2IF bit is
set, causing a CCP interrupt (if enabled).
TABLE 9-3:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Name
Bit 7
GIE
PSPIF
(1)
OSFIF
PSPIE
(1)
OSFIE
Bit 6
PEIE
ADIF
CMIF
ADIE
CMIE
Bit 5
TMR0IE
RCIF
LVDIF
RCIE
LVDIE
Bit 4
INT0IE
TXIF
—
TXIE
—
Bit 3
RBIE
SSPIF
BCLIF
SSPIE
BCLIE
Bit 2
TMR0IF
CCP1IF
—
—
Bit 1
INT0IF
TMR2IF
CCP3IF
CCP3IE
Bit 0
RBIF
Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh, INTCON
10Bh,18Bh
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
95h
96h
97h
Legend:
Note 1:
PIR1
PIR2
PIE1
PIE2
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCPR3L
CCPR3H
CCP3CON
0000 000x 0000 000u
TMR1IF
0000 0000 0000 0000
CCP2IF
000- 0-00 000- 0-00
TMR1IE
0000 0000 0000 0000
CCP2IE
000- 0-00 000- 0-00
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1IE TMR2IE
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
—
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
—
—
CCP1X
CCP1Y
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
—
—
CCP2X
CCP2Y
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
—
—
CCP3X
CCP3Y
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
-000 0000 -uuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP3M3 CCP3M2 CCP3M1 CCP3M0
--00 0000 --00 0000
x
= unknown,
u
= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
The PSP is not implemented on the PIC16F737/767 devices; always maintain these bits clear.
DS30498C-page 90
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
