PIC16F7X7
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
9.6.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
EQUATION 9-3:
Resolution
=
F
OSC
log F
PWM
(
)
bits
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 9-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
OSC
= 20 MHz)
1.22 kHz
16
0xFF
10
4.88 kHz
4
0xFF
10
19.53 kHz
1
0xFF
10
78.12 kHz
1
0x3F
8
156.3 kHz
1
0x1F
7
208.3 kHz
1
0x17
6.6
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 9-5:
Address
Name
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7
GIE
PSPIF
(1)
OSFIF
PSPIE
(1)
OSFIE
Bit 6
PEIE
ADIF
CMIF
ADIE
CMIE
Bit 5
TMR0IE
RCIF
LVDIF
RCIE
LVDIE
Bit 4
INT0IE
TXIF
—
TXIE
—
Bit 3
RBIE
SSPIF
BCLIF
SSPIE
BCLIE
Bit 2
TMR0IF
CCP1IF
—
CCP1IE
—
Bit 1
INT0IF
TMR2IF
CCP3IF
TMR2IE
CCP3IE
Bit 0
RBIF
Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh, INTCON
10Bh,18Bh
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
1Bh
1Ch
1Dh
95h
96h
97h
Legend:
Note 1:
PIR1
PIR2
PIE1
PIE2
TRISC
TMR2
PR2
T2CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCPR3L
CCPR3H
CCP3CON
0000 000x 0000 000u
TMR1IF
0000 0000 0000 0000
CCP2IF
000- 0-00 000- 0-00
TMR1IE
0000 0000 0000 0000
CCP2IE
000- 0-00 000- 0-00
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
PORTC Data Direction Register
Timer2 Module Register
Timer2 Period Register
—
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
—
—
CCP1X
CCP1Y
CCP1M3
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
—
—
CCP3X
CCP3Y
CCP3M3
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M2 CCP2M1 CCP2M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP3M2 CCP3M1 CCP3M0
--00 0000 --00 0000
x
= unknown,
u
= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
DS30498C-page 92
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
