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PIC16F777-I/PT 参数 Datasheet PDF下载

PIC16F777-I/PT图片预览
型号: PIC16F777-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X7  
SSPSR is the shift register used for shifting data in or  
out. SSPBUF is the buffer register to which data bytes  
are written to or read from.  
10.3.1  
REGISTERS  
The MSSP module has four registers for SPI mode  
operation. These are:  
In receive operations, SSPSR and SSPBUF together  
create a double-buffered receiver. When SSPSR  
receives a complete byte, it is transferred to SSPBUF  
and the SSPIF interrupt is set.  
• MSSP Control Register (SSPCON)  
• MSSP Status Register (SSPSTAT)  
• Serial Receive/Transmit Buffer (SSPBUF)  
• MSSP Shift Register (SSPSR) – Not directly  
accessible  
During transmission, the SSPBUF is not double-  
buffered. A write to SSPBUF will write to both SSPBUF  
and SSPSR.  
SSPCON and SSPSTAT are the control and status  
registers in SPI mode operation. The SSPCON  
register is readable and writable. The lower 6 bits of  
the SSPSTAT are read-only. The upper two bits of the  
SSPSTAT are read/write.  
REGISTER 10-1: SSPSTAT: MSSP STATUS (SPI MODE) REGISTER (ADDRESS 94h)  
R/W-0  
SMP  
R/W-0  
CKE  
R-0  
D/A  
R-0  
P
R-0  
S
R-0  
R-0  
UA  
R-0  
BF  
R/W  
bit 7  
bit 0  
bit 7  
bit 6  
SMP: Sample bit  
SPI Master mode:  
1= Input data sampled at end of data output time  
0= Input data sampled at middle of data output time  
SPI Slave mode:  
SMP must be cleared when SPI is used in Slave mode.  
CKE: SPI Clock Edge Select bit  
1= Transmit occurs on transition from active to Idle clock state  
0= Transmit occurs on transition from Idle to active clock state  
Note:  
Polarity of clock state is set by the CKP bit (SSPCON1<4>).  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
D/A: Data/Address bit  
Used in I2C mode only.  
P: Stop bit  
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.  
S: Start bit  
Used in I2C mode only.  
R/W: Read/Write bit Information  
Used in I2C mode only.  
UA: Update Address bit  
Used in I2C mode only.  
BF: Buffer Full Status bit (Receive mode only)  
1= Receive complete, SSPBUF is full  
0= Receive not complete, SSPBUF is empty  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
DS30498C-page 94  
2004 Microchip Technology Inc.  
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