PIC16F7X7
9.5.1
CCP PIN CONFIGURATION
9.5.4
SPECIAL EVENT TRIGGER
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
9.5.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Note:
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1<0>).
9.5.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCP1IF or CCP2IF bit is
set, causing a CCP interrupt (if enabled).
TABLE 9-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
all other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF 0000 000x 0000 000u
(1)
0Ch
0Dh
8Ch
8Dh
87h
PIR1
PSPIF
ADIF
RCIF
LVDIF
RCIE
TXIF
—
SSPIF
BCLIF
SSPIE
BCLIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP3IF CCP2IF 000- 0-00 000- 0-00
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
OSFIF CMIF
—
(1)
PIE1
PSPIE
ADIE
TXIE
—
PIE2
OSFIE CMIE
LVDIE
—
CCP3IE CCP2IE 000- 0-00 000- 0-00
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
0Fh
10h
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
15h
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM Register 1 (MSB)
17h
CCP1CON
CCPR2L
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh
1Ch
1Dh
95h
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register 2 (MSB)
CCP2CON
CCPR3L
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Capture/Compare/PWM Register 3 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
96h
CCPR3H Capture/Compare/PWM Register 3 (MSB)
CCP3CON CCP3X
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
97h
—
—
CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
Legend:
Note 1: The PSP is not implemented on the PIC16F737/767 devices; always maintain these bits clear.
DS30498C-page 90
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
