PIC16F7X7
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
9.6.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
EQUATION 9-3:
5. Configure the CCP1 module for PWM operation.
FOSC
log( )
FPWM
Resolution
bits
=
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 9-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 9-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
0Ch
0Dh
8Ch
8Dh
87h
PIR1
PSPIF(1)
OSFIF
PSPIE(1)
ADIF
CMIF
ADIE
CMIE
RCIF
LVDIF
RCIE
LVDIE
TXIF
—
SSPIF
BCLIF
SSPIE
BCLIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP3IF CCP2IF 000- 0-00 000- 0-00
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
PIE1
TXIE
—
PIE2
OSFIE
—
CCP3IE CCP2IE 000- 0-00 000- 0-00
1111 1111 1111 1111
TRISC
PORTC Data Direction Register
Timer2 Module Register
Timer2 Period Register
11h
TMR2
0000 0000 0000 0000
92h
PR2
1111 1111 1111 1111
12h
T2CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCPR3L
CCPR3H
CCP3CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh
1Ch
1Dh
95h
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
96h
97h
—
—
CCP3X
CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
Legend:
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
DS30498C-page 92
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
