PIC16C745/765
FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
08h
09h
89h
0Ch
8Ch
9Fh
0Bh
PORTD
PORTE
Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
(2)
—
IBF
—
—
—
—
RE2
RE1
RE0
(2)
TRISE
PIR1
PIE1
OBF IBOV PSPMODE
—
PORTE Data Direction Bits
(1)
(1)
PSPIF
PSPIE
—
ADIF RCIF
ADIE RCIE
TXIF
TXIE
—
USBIF CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
ADCON1
INTCON
—
—
—
PCFG2
T0IF
PCFG1
INTF
PCFG0 ---- -000 ---- -000
RBIF 0000 000x 0000 000u
GIE
PEIE T0IE
INTE
RBIE
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear.
2: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 41
MICROCHIP [ MICROCHIP ]
