PIC16C745/765
5.4
PORTD and TRISD Registers
FIGURE 5-6: PORTD BLOCK DIAGRAM
VDD
Note: The PIC16C745 does not provide PORTD.
The PORTD and TRISD registers are
reserved. Always maintain these bits clear.
Data
Bus
D
Q
WR
PORT
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configured as an input or
output.
I/O pin
CK
Data Latch
D
Q
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
WR
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
EN
RD PORT
TABLE 5-7:
PORTD FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
(1)
RD0
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
CMOS Bi-directional I/O
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
(1)
PSP0
RD1
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PSP1
RD2
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP2
RD3
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP3
RD4
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP4
RD5
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP5
RD6
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP6
RD7
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP7
—
Parallel Slave Port data input
Legend:
OD = open drain, ST = Schmitt Trigger
Note 1: PIC16C765 only.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
08h
88h
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PORTD
(1)
PORTD Data Direction Register
TRISD
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.
Note 1: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 37
MICROCHIP [ MICROCHIP ]
