PIC16C745/765
The PSA and PS<2:0> bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio.
6.2
Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the watchdog timer. The prescaler is not
readable or writable.
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
6.3
Prescaler
To avoid an unintended device RESET, the following
instruction sequence (shown in Example 6-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
module means that there is no prescaler for the watch-
dog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 6-1).
EXAMPLE 6-1: CHANGING PRESCALER (TIMER0→WDT)
1) BSF
STATUS, RP0
;Bank1
2) MOVLW b’xx0x0xxx’
3) MOVWF OPTION_REG
;Select clock source and prescale value of
Lines 2 and 3 do
NOT have to be
;other than 1:1
included if the final
desired prescale
value is other than
1:1. If 1:1 is the final
desired value, then a
temporary prescale
value is set in lines 2
and 3 and the final
prescale value will
be set in lines 10
and 11.
4) BCF
5) CLRF
6) BSF
STATUS, RP0
TMR0
;Bank0
;Clear TMR0 and prescaler
STATUS, RP1
;Bank1
7) MOVLW b’xxxx1xxx’
8) MOVWF OPTION_REG
9) CLRWDT
;Select WDT, do not change prescale value
;
;Clears WDT and prescaler
10) MOVLW b’xxxx1xxx’
11) MOVWF OPTION_REG
;Select new prescale value and WDT
;
12) BCF
STATUS, RP0
;Bank0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
INTCON
OPTION_REG RBPU INTEDG T0CS
Timer0 module’s register
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
GIE PEIE T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
81h,181h
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS41124A-page 44
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
