PIC16C745/765
REGISTER 5-1: PORTE DATA DIRECTION CONTROL REGISTER(1) (TRISE: 89h)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7 :
bit 6:
bit 5:
bit 4:
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel slave port mode
0= General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as '0'
PORTE Data Direction Bits
TRISE2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1:
bit 0:
TRISE1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
TRISE0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
Note 1: PIC16C765 only.
TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
09h
89h
9Fh
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
0000 -111 0000 -111
---- -000 ---- -000
PORTE
(1)
IBF OBF IBOV PSPMODE
PORTE Data Direction Bits
PCFG2 PCFG1 PCFG0
TRISE
ADCON1
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 39
MICROCHIP [ MICROCHIP ]
