PIC16C745/765
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
This interrupt-on-mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a power-on reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
FIGURE 5-3: BLOCK DIAGRAM OF RB<3:0>
PINS
VDD
VDD
RB0/INT is discussed in detail in Section 13.5.1.
RBPU(1)
weak
pull-up
P
FIGURE 5-4: BLOCK DIAGRAM OF
RB<7:4> PINS
Data Latch
Data Bus
WR Port
D
Q
VDD
VDD
I/O
pin
RBPU(1)
weak
P
CK
TRIS Latch
pull-up
Data Latch
Data Bus
D
Q
D
Q
TTL
Input
I/O
pin
WR TRIS
WR Port
CK
Buffer
CK
TRIS Latch
D
Q
RD TRIS
RD Port
WR TRIS
TTL
Input
Buffer
CK
Q
D
ST
Buffer
EN
RD TRIS
RD Port
Latch
RB0/INT
Q
Q
D
Schmitt Trigger
Buffer
RD Port
EN
Q1
Set RBIF
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
D
From other
RB<7:4> pins
RD Port
Q3
Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins (of RB<7:4>) are
compared with the value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
EN
RB<7:6> in serial programming mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 33
MICROCHIP [ MICROCHIP ]
