PIC16C745/765
FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C745/765)
RE2/CS
RE0/RD
RE1/WR
65
RD<7:0>
62
64
63
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS
Param No. Sym
Characteristic
Min Typ†
Max
—
Units
ns
Conditions
62*
TDTV2WRH Data in valid before WR↑ or CS↑ (setup time)
TWRH2DTI WR↑ or CS↑ to data–in invalid (hold time)
20
20
35
—
10
—
—
—
—
—
63*
—
ns
—
ns
64
TRDL2DTV RD↓ and CS↓ to data–out valid
TRDH2DTI RD↑ or CS↑ to data–out invalid
80
30
ns
65*
ns
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41124A-page 136
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
