PIC16C745/765
FIGURE 16-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 16-2 for load conditions.
122
TABLE 16-8: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max
Units Conditions
120*
TCKH2DTV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
—
—
—
—
—
—
—
80
ns
ns
ns
ns
ns
ns
—
—
—
—
—
100
45
121*
122*
TCKRF
TDTRF
Clock out rise time and fall time (Master Mode)
Data out rise time and fall time
50
45
50
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 16-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin
125
RC7/RX/DT pin
126
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-9: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max
Units Conditions
125*
TDTV2CKL
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
—
—
ns
ns
126*
TCKL2DTL
Data hold after CK ↓ (DT hold time)
15
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 137
MICROCHIP [ MICROCHIP ]
