PIC16C745/765
FIGURE 16-5: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
FINT
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max
Units Conditions
10*
TOSH2CKL OSC1↑ to CLKOUT↓
TOSH2CKH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
—
10
—
10
—
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
11*
12*
200
100
100
TCKR
CLKOUT rise time
13*
TCKF
CLKOUT fall time
14*
TCKL2IOV
TIOV2CKH
TCKH2IOI
TOSH2IOV
TOSH2IOI
CLKOUT ↓ to Port out valid
Port in valid before CLKOUT ↑
Port in hold after CLKOUT ↑
OSC1↑ (Q1 cycle) to Port out valid
0.5 TCY + 20
15*
TOSC + 200
—
—
16*
0
—
17*
150
—
18*
OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold
100
200
0
time)
18A*
19*
—
TIOV2OSH Port input valid to OSC1↑ (I/O in setup time)
—
20*
TIOR
Port output rise time
—
40
80
40
80
20A*
21*
—
TIOF
Port output fall time
—
21A*
—
22††* TINP
23††* TRBP
INT pin high or low time
TCY
TCY
—
—
—
—
ns
ns
RB<7:4> change INT high or low time
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
2: FINT = OSC1 when PLL
DS41124A-page 132
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
