PIC16C745/765
FIGURE 16-13: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
134
(TOSC/2) (1)
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 16-11: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic
A/D clock period
Min
1.6
Typ†
Max
Units Conditions
130
TAD
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
2.0
TOSC based,
2.5V ≤ VREF ≤ 5.5V
2.0
3.0
11
4.0
6.0
—
6.0
9.0
11
µs
µs
A/D RC Mode
A/D RC Mode
131
132
TCNV Conversion time (not including S/H time)
TAD
(Note 1)
TACQ Acquisition time
5*
—
—
µs
The minimum time is the ampli-
fier settling time. This may be
used if the “new” input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134
135
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
TSWC Switching from convert → sample time
1.5 §
—
—
TAD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 for min conditions.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 139
MICROCHIP [ MICROCHIP ]
