PIC16C745/765
16.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-3: EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
4
Q4
Q1
OSC1
3
3
1
4
2
CLKOUT
FIGURE 16-4: CLOCK MULTIPLIER (PLL) PHASE RELATIONSHIP
OSC1/
CLKIN
FINT
Note 1: FINT represents the internal clock signal. FINT equals FOSC or CLKIN if the PLL is disabled. FINT
equals 4x FOSC or 4x CLKIN if the PLL is enabled. TCY is always 4/FINT. FINT is OSC1 pin in EC
mode, PLL disabled.
2: FINT = OSC1 in EC mode with PLL disabled.
DS41124A-page 130
Advanced Information
1999 Microchip Technology Inc.