PIC16C745/765
TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
24
Units Conditions
1A
FOSC
External CLKIN Frequency
(Note 1)
24
6
—
—
—
—
—
—
—
—
—
—
MHz EC osc mode
MHz E4 osc mode
MHz HS osc mode
MHz H4 osc mode
6
24
6
Oscillator Frequency
(Note 1)
24
6
1
TOSC
TCY
External CLKIN Period
(Note 1)
41
167
41
167
167
41
167
41
167
DC
—
ns
ns
ns
ns
ns
ns
EC osc modes
E4 osc mode
HS osc modes
H4 osc mode
TCY = 4/FINT
EC oscillator
Oscillator Period
(Note 1)
2
Instruction Cycle Time (Note 1)
3*
TOSL,
TOSH
External Clock in (OSC1) High or Low TBD
Time
4*
TOSR, External Clock in (OSC1) Rise or Fall TBD
TOSF Time
—
25
ns
EC oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period when the PLL is enabled, or the input
oscillator time-base period divided by 4 when the PLL is disabled. All specified values are based on characterization data
for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these
specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices
are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input
is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 131
MICROCHIP [ MICROCHIP ]
