PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31
F80h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
F81h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
F82h(2)
F83h(2)
F84h(2)
F85h(2)
F86h(2)
F87h(2)
F88h(2)
F89h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
F8Ah(1),(2 PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
)
F8Bh(2)
INTCON
—
GIE
PEIE TMR0IE INTE IOCIE TMR0IF
INTF
DC
IOCIF
C
0000 000x 0000 000u
F8Ch
—
FE3h
Unimplemented
—
—
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
STATUS_
Z
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SHAD
WREG_
SHAD
BSR_
Working Register Normal (Non-ICD) Shadow
Bank Select Register Normal (Non-ICD) Shadow
Program Counter Latch High Register Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow
Unimplemented
SHAD
PCLATH_
SHAD
FSR0L_
SHAD
FSR0H_
SHAD
FSR1L_
SHAD
FSR1H_
SHAD
FECh
FEDh
FEEh
—
—
—
—
—
—
Current Stack pointer
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
STKPTR
TOSL
Top of Stack Low byte
Top of Stack High byte
FEFh
—
TOSH
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 45
MICROCHIP [ MICROCHIP ]
