PIC16F/LF1946/47
TABLE 28-3: PIC16F/LF1946/47 ENHANCED INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0110 0010
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSR, n = FSR0 or FSR1
Move Indirect to W, n = FSR0 or FSR1, with
pre/post inc/dec modifier.
Move INDFn to W, Indexed Indirect.
Move W to Indirect, n = FSR0 or FSR1, with
pre/post inc/dec modifier.
1
1
1
1
1
11 0001 0nkk kkkk
00 0000 0001 0nmm
11 1111 0nkk kkkk
00 0000 0001 1nmm
11 1111 1nkk kkkk
MOVIW
n
Z
Z
2
2
2
2
MOVWI
k[n]
n
k[n]
Move W to INDFn, Indexed Indirect.
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
DS41414A-page 370
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
