PIC16F/LF1946/47
REGISTER 12-18: LATE: PORTE DATA LATCH REGISTER
R/W-x/u
LATE7
R/W-x/u
LATE6
R/W-x/u
LATE5
R/W-x/u
LATE4
R/W-x/u
LATE3
R/W-x/u
LATE2
R/W-x/u
LATE1
R/W-x/u
LATE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
LATE<7:0>: PORTE Output Latch Value bits(1)
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of
actual I/O pin values.
REGISTER 12-19: ANSELE: PORTE ANALOG SELECT REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSE7
ANSE6
ANSE5
ANSE4
ANSE3
ANSE2
ANSE1
ANSE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
bit 7-0
ANSE<7:0>: Analog Select between Analog or Digital Function on Pins RE<7:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3CSEL
ANSE7
P3BSEL
P2DSEL
ANSE5
P2CSEL
ANSE4
P2BSEL CCP2SEL
P1CSEL
ANSE1
P1BSEL
ANSE0
APFCON
ANSELE
CCPxCON
LATE
122
137
229
137
329
331
333
ANSE6
ANSE3
LATE3
ANSE2
LATE2
(1)
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
LATE7
LCDEN
LCDIRE
SE31
LATE6
SLPEN
LCDIRS
SE30
LATE5
WERR
LCDIRI
SE29
LATE4
—
LATE1
LATE0
LCDCON
LCDREF
LCDSE2
PORTE
LMUX<1:0>
CS<1:0>
—
VLCD3PE VLCD2PE VLCD1PE
—
SE28
RE4
SE27
RE3
SE26
RE2
SE25
RE1
SE24
RE0
RE7
RE6
RE5
136
136
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Applies to ECCP modules only.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 137
MICROCHIP [ MICROCHIP ]
