PIC16F/LF1946/47
REGISTER 12-9: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
WPUB7
R/W-1/1
WPUB6
R/W-1/1
WPUB5
R/W-1/1
WPUB4
R/W-1/1
WPUB3
R/W-1/1
WPUB2
R/W-1/1
WPUB1
R/W-1/1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
WPUB<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
IOCBP6
IOCBN6
IOCBF6
LATB6
SE14
TMR0IE
IOCBP5
IOCBN5
IOCBF5
LATB5
SE13
INTE
IOCBP4
IOCBN4
IOCBF4
LATB4
SE12
IOCIE
IOCBP3
IOCBN3
IOCBF3
LATB3
SE11
TMR0IF
IOCBP2
IOCBN2
IOCBF2
LATB2
SE10
INTF
IOCBP1
IOCBN1
IOCBF1
LATB1
SE9
IOCIF
IOCBP0
IOCBN0
IOCBF0
LATB0
SE8
89
IOCBP
IOCBN
IOCBF
LATB
IOCBP7
IOCBN7
IOCBF7
LATB7
SE15
148
148
148
127
333
333
333
189
127
200
127
128
LCDSE1
LCDSE3
LCDSE4
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24
SE39
SE38
SE37
SE36
SE35
SE34
SE33
SE32
OPTION_REG WPUEN
INTEDG
RB6
TMR0CS TMR0SE
PSA
PS<2:0>
RB1
PORTB
T1GCON
TRISB
RB7
RB5
RB4
RB3
RB2
RB0
TMR1GE T1GPOL
T1GTM
TRISB5
WPUB5
T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
TRISB7
WPUB7
TRISB6
WPUB6
TRISB4
WPUB4
TRISB3
WPUB3
TRISB2
WPUB2
TRISB1
WPUB1
TRISB0
WPUB0
WPUB
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
DS41414A-page 128
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
