PIC16C62B/72A
8.3.2
MASTER OPERATION
8.3.3
MULTI-MASTER OPERATION
Master operation is supported in firmware using inter-
rupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared by a reset or when the SSP module is dis-
abled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I2C bus may be taken when the P bit is set, or the
bus is idle and both the S and P bits are clear.
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In master operation, the SCL and SDA lines are manip-
ulated in software by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So when
transmitting data, a ’1’ data bit must have the
TRISC<4> bit set (input) and a ’0’ data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
• Byte transfer completed
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see AN554
- Software Implementation of I2C Bus Master.
For more information on master operation, see AN578
- Use of the SSP Module in the of I2C Multi-Master
Environment.
TABLE 8-3
REGISTERS ASSOCIATED WITH I2C OPERATION
Value on
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh, 8Bh
0Ch
8Ch
13h
INTCON
PIR1
GIE
—
PEIE
T0IE
—
INTE
—
RBIE
T0IF
INTF
RBIF
ADIF
SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
PIE1
ADIE
—
—
—
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
2
93h
SSPADD Synchronous Serial Port (I C mode) Address Register
14h
SSPCON
SSPSTAT
TRISC
WCOL
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
(1)
(1)
94h
SMP
CKE
D/A
P
S
R/W
UA
BF
PORTC Data Direction register
87h
1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
2
Note 1: Maintain these bits clear in I C mode.
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 45
MICROCHIP [ MICROCHIP ]
