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PIC16C62B-04/SO 参数 Datasheet PDF下载

PIC16C62B-04/SO图片预览
型号: PIC16C62B-04/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28引脚8位CMOS微控制器 [28-Pin 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 120 页 / 1994 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C62B/72A  
8.3.1.3  
TRANSMISSION  
shifted out on the falling edge of the SCL input. This  
ensures that the SDA signal is valid during the SCL  
high time (Figure 8-4).  
When the R/W bit of the incoming address byte is set  
and an address match occurs, the R/W bit of the  
SSPSTAT register is set. The received address is  
loaded into the SSPBUF register. The ACK pulse will  
be sent on the ninth bit and the CKP will be cleared by  
hardware, holding SCL low. Slave devices cause the  
master to wait by holding the SCL line low. The transmit  
data is loaded into the SSPBUF register, which in turn  
loads the SSPSR register. When bit CKP (SSP-  
CON<4>) is set, pin RC3/SCK/SCL releases SCL.  
When the SCL line goes high, the master may resume  
operating the SCL line and receiving data. The master  
must monitor the SCL pin prior to asserting another  
clock pulse. The slave devices may be holding off the  
master by stretching the clock. The eight data bits are  
An SSP interrupt is generated for each data transfer  
byte. Flag bit SSPIF must be cleared in software, and  
the SSPSTAT register used to determine the status of  
the byte. Flag bit SSPIF is set on the falling edge of the  
ninth clock pulse.  
As a slave-transmitter, the ACK pulse from the master-  
receiver is latched on the rising edge of the ninth SCL  
input pulse. If the SDA line was high (not ACK), then the  
data transfer is complete. When the ACK is latched by  
the slave, the slave logic is reset (resets SSPSTAT reg-  
ister) and the slave then monitors for another occur-  
rence of the START bit. If the SDA line was low (ACK),  
the transmit data must be loaded into the SSPBUF reg-  
ister, which also loads the SSPSR register. Then pin  
RC3/SCK/SCL should be enabled by setting bit CKP.  
FIGURE 8-4: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)  
Receiving Address  
R/W = 1  
ACK  
Transmitting Data  
ACK  
9
SDA  
SCL  
A7 A6 A5 A4 A3 A2 A1  
D7 D6 D5 D4 D3 D2 D1 D0  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SCL held low  
while CPU  
responds to SSPIF  
Data in  
sampled  
cleared in software  
SSPIF (PIR1<3>)  
BF (SSPSTAT<0>)  
From SSP interrupt  
service routine  
SSPBUF is written in software  
CKP (SSPCON<4>)  
Set bit after writing to SSPBUF  
(the SSPBUF must be written-to  
before the CKP bit can be set)  
DS35008B-page 44  
Preliminary  
1999 Microchip Technology Inc.