欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC12C508A-04/P 参数 Datasheet PDF下载

PIC12C508A-04/P图片预览
型号: PIC12C508A-04/P
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚, 8位CMOS微控制器 [8-Pin, 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 113 页 / 1604 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC12C508A-04/P的Datasheet PDF文件第41页浏览型号PIC12C508A-04/P的Datasheet PDF文件第42页浏览型号PIC12C508A-04/P的Datasheet PDF文件第43页浏览型号PIC12C508A-04/P的Datasheet PDF文件第44页浏览型号PIC12C508A-04/P的Datasheet PDF文件第46页浏览型号PIC12C508A-04/P的Datasheet PDF文件第47页浏览型号PIC12C508A-04/P的Datasheet PDF文件第48页浏览型号PIC12C508A-04/P的Datasheet PDF文件第49页  
PIC12C5XX  
8.9  
Power-Down Mode (SLEEP)  
8.10  
Program Verification/Code Protection  
A device may be powered down (SLEEP) and later  
powered up (Wake-up from SLEEP).  
If the code protection bit has not been programmed,  
the on-chip program memory can be read out for  
verification purposes.  
8.9.1  
SLEEP  
The first 64 locations can be read by the PIC12C5XX  
regardless of the code protection bit setting.  
The Power-Down mode is entered by executing a  
SLEEPinstruction.  
The last memory location cannot be read if code pro-  
tection is enabled on the PIC12C508/509.  
If enabled, the Watchdog Timer will be cleared but  
keeps running, the TO bit (STATUS<4>) is set, the PD  
bit (STATUS<3>) is cleared and the oscillator driver is  
turned off. The I/O ports maintain the status they had  
before the SLEEP instruction was executed (driving  
high, driving low, or hi-impedance).  
The last memory location can be read regardless of the  
code protection bit setting on the PIC12C508A/509A/  
CR509A/CE518/CE519.  
8.11  
ID Locations  
It should be noted that a RESET generated by a WDT  
time-out does not drive the MCLR pin low.  
Four memory locations are designated as ID locations  
where the user can store checksum or other code-  
identification numbers. These locations are not  
accessible during normal execution but are readable  
and writable during program/verify.  
For lowest current consumption while powered down,  
the T0CKI input should be at VDD or VSS and the GP3/  
MCLR/VPP pin must be at a logic high level (VIHMC) if  
MCLR is enabled.  
Use only the lower 4 bits of the ID locations and  
always program the upper 8 bits as ’0’s.  
8.9.2  
WAKE-UP FROM SLEEP  
The device can wake-up from SLEEP through one of  
the following events:  
1. An external reset input on GP3/MCLR/VPP pin,  
when configured as MCLR.  
2. A Watchdog Timer time-out reset (if WDT was  
enabled).  
3. A change on input pin GP0, GP1, or GP3/  
MCLR/VPP when wake-up on change is  
enabled.  
These events cause a device reset. The TO, PD, and  
GPWUF bits can be used to determine the cause of  
device reset. The TO bit is cleared if a WDT time-out  
occurred (and caused wake-up). The PD bit, which is  
set on power-up, is cleared when SLEEP is invoked.  
The GPWUF bit indicates a change in state while in  
SLEEP at pins GP0, GP1, or GP3 (since the last time  
there was a file or bit operation on GP port).  
Caution: Right before entering SLEEP, read the  
input pins. When in SLEEP, wake up  
occurs when the values at the pins change  
from the state they were in at the last  
reading. If a wake-up on change occurs  
and the pins are not read before  
reentering SLEEP, a wake up will occur  
immediately even if no pins change while  
in SLEEP mode.  
The WDT is cleared when the device wakes from  
sleep, regardless of the wake-up source.  
1999 Microchip Technology Inc.  
DS40139E-page 45  
 复制成功!