PIC12C5XX
8.6.1
WDT PERIOD
8.6.2
WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-to-
part process variations (see DC specs).
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 8-5)
0
M
Postscaler
Postscaler
1
Watchdog
Timer
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
Configuration Bit
To Timer0 (Figure 8-4)
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 8-6:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-On
Reset
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
PS1 PS0
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
1111 1111
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, —= unimplemented, read as ’0’, u= unchanged
1999 Microchip Technology Inc.
DS40139E-page 43
MICROCHIP [ MICROCHIP ]
