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PIC12C508A-04/P 参数 Datasheet PDF下载

PIC12C508A-04/P图片预览
型号: PIC12C508A-04/P
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚, 8位CMOS微控制器 [8-Pin, 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 113 页 / 1604 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12C5XX  
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME  
V1  
VDD  
MCLR  
INTERNAL POR  
TDRT  
DRT TIME-OUT  
INTERNAL RESET  
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In  
this example, the chip will reset properly if, and only if, V1 VDD min.  
8.5  
Device Reset Timer (DRT)  
8.6  
Watchdog Timer (WDT)  
In the PIC12C5XX, DRT runs from RESET and varies  
based on oscillator selection (see Table 8-5.)  
The Watchdog Timer (WDT) is a free running on-chip  
RC oscillator which does not require any external  
components. This RC oscillator is separate from the  
external RC oscillator of the GP5/OSC1/CLKIN pin  
and the internal 4 MHz oscillator. That means that the  
WDT will run even if the main processor clock has  
been stopped, for example, by execution of a SLEEP  
instruction. During normal operation or SLEEP, a WDT  
reset or wake-up reset generates a device RESET.  
The DRT operates on an internal RC oscillator. The  
processor is kept in RESET as long as the DRT is  
active. The DRT delay allows VDD to rise above VDD  
min., and for the oscillator to stabilize.  
Oscillator circuits based on crystals or ceramic  
resonators require a certain time after power-up to  
establish a stable oscillation. The on-chip DRT keeps  
the device in a RESET condition for approximately 18  
ms after MCLR has reached a logic high (VIHMCLR)  
level. Thus, programming GP3/MCLR/VPP as MCLR  
and using an external RC network connected to the  
MCLR input is not required in most cases, allowing for  
savings in cost-sensitive and/or space restricted  
applications, as well as allowing the use of the GP3/  
MCLR/VPP pin as a general purpose input.  
The TO bit (STATUS<4>) will be cleared upon a  
Watchdog Timer reset.  
The WDT can be permanently disabled by  
programming the configuration bit WDTE as a ’0’  
(Section 8.1). Refer to the PIC12C5XX Programming  
Specifications to determine how to access the  
configuration word.  
TABLE 8-5:  
DRT (DEVICE RESET TIMER  
PERIOD)  
The Device Reset time delay will vary from chip to chip  
due to VDD, temperature, and process variation. See  
AC parameters for details.  
Oscillator  
Configuration  
Subsequent  
POR Reset  
Resets  
The DRT will also be triggered upon a Watchdog  
Timer time-out. This is particularly important for  
applications using the WDT to wake from SLEEP  
mode automatically.  
IntRC &  
ExtRC  
18 ms (typical) 300 µs (typical)  
XT & LP  
18 ms (typical)  
18 ms (typical)  
DS40139E-page 42  
1999 Microchip Technology Inc.  
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