PIC12F683
2.2.2.4
PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
EEIE
R/W-0
ADIE
R/W-0
U-0
—
R/W-0
CMIE
R/W-0
OSFIE
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
bit 7
bit 6
bit 5
EEIE: EE Write Complete Interrupt Enable bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 4
bit 3
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1= Enables the Comparator 1 interrupt
0= Disables the Comparator 1 interrupt
bit 2
bit 1
bit 0
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the oscillator fail interrupt
0= disables the oscillator fail interrupt
TMR2IE: Timer 2 to PR2 Match Interrupt Enable bit
1= Enables the Timer 2 to PR2 match interrupt
0= Disables the Timer 2 to PR2 match interrupt
TMR1IE: Timer 1 Overflow Interrupt Enable bit
1= Enables the Timer 1 overflow interrupt
0= Disables the Timer 1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41211B-page 14
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
