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PIC12F683-I/SNG 参数 Datasheet PDF下载

PIC12F683-I/SNG图片预览
型号: PIC12F683-I/SNG
PDF下载: 下载PDF文件 查看货源
内容描述: [8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO8, 3.90 MM, PLASTIC, SOIC-8]
分类和应用: 闪存微控制器
文件页数/大小: 148 页 / 2282 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F683  
The stack operates as a circular buffer. This means that  
after the stack has been PUSHed eight times, the ninth  
push overwrites the value that was stored from the first  
push. The tenth push overwrites the second push (and  
so on).  
2.3  
PCL and PCLATH  
The Program Counter (PC) is 13 bits wide. The low byte  
comes from the PCL register, which is a readable and  
writable register. The high byte (PC<12:8>) is not  
directly readable or writable and comes from PCLATH.  
On any Reset, the PC is cleared. Figure 2-3 shows the  
two situations for the loading of the PC. The upper  
example in Figure 2-3 shows how the PC is loaded on a  
write to PCL (PCLATH<4:0> PCH). The lower exam-  
ple in Figure 2-3 shows how the PC is loaded during a  
CALLor GOTOinstruction (PCLATH<4:3> PCH).  
Note 1: There are no Status bits to indicate stack  
overflow or stack underflow conditions.  
2: There are no instructions/mnemonics  
called PUSH or POP. These are actions  
that occur from the execution of the  
CALL, RETURN, RETLW and RETFIE  
instructions or the vectoring to an  
interrupt address.  
FIGURE 2-3:  
LOADING OF PC IN  
DIFFERENT SITUATIONS  
2.4  
Indirect Addressing, INDF and  
FSR Registers  
PCH  
PCL  
Instruction with  
PCL as  
12  
8
7
0
Destination  
PC  
The INDF register is not a physical register. Addressing  
the INDF register will cause indirect addressing.  
8
PCLATH<4:0>  
PCLATH  
5
ALU Result  
Indirect addressing is possible by using the INDF  
register. Any instruction using the INDF register  
actually accesses data pointed to by the File Select  
Register (FSR). Reading INDF itself indirectly will  
produce 00h. Writing to the INDF register indirectly  
results in a no operation (although Status bits may be  
affected). An effective 9-bit address is obtained by  
concatenating the 8-bit FSR register and the IRP bit  
(Status<7>), as shown in Figure 2-4.  
PCH  
12 11 10  
PC  
PCL  
8
7
0
GOTO, CALL  
PCLATH<4:3>  
PCLATH  
11  
2
OPCODE<10:0>  
A simple program to clear RAM location 20h-2Fh using  
indirect addressing is shown in Example 2-1.  
2.3.1  
COMPUTED GOTO  
EXAMPLE 2-1:  
INDIRECT ADDRESSING  
A computed GOTOis accomplished by adding an offset  
to the program counter (ADDWF PCL). When perform-  
ing a table read using a computed GOTOmethod, care  
should be exercised if the table location crosses a PCL  
memory boundary (each 256-byte block). Refer to the  
Application Note AN556, “Implementing a Table Read”  
(DS00556).  
MOVLW  
MOVWF  
CLRF  
INCF  
BTFSS  
GOTO  
0x20  
FSR  
INDF  
FSR  
FSR,4  
NEXT  
;initialize pointer  
;to RAM  
;clear INDF register  
;inc pointer  
;all done?  
;no clear next  
;yes continue  
NEXT  
CONTINUE  
2.3.2  
STACK  
The PIC12F683 family has an 8-level x 13-bit wide  
hardware stack (see Figure 2-1). The stack space is  
not part of either program or data space and the stack  
pointer is not readable or writable. The PC is PUSHed  
onto the stack when a CALLinstruction is executed or  
an interrupt causes a branch. The stack is POPed in  
the event of a RETURN,RETLWor a RETFIEinstruction  
execution. PCLATH is not affected by a PUSH or POP  
operation.  
2004 Microchip Technology Inc.  
Preliminary  
DS41211B-page 17