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PIC12F683-I/SNG 参数 Datasheet PDF下载

PIC12F683-I/SNG图片预览
型号: PIC12F683-I/SNG
PDF下载: 下载PDF文件 查看货源
内容描述: [8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO8, 3.90 MM, PLASTIC, SOIC-8]
分类和应用: 闪存微控制器
文件页数/大小: 148 页 / 2282 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F683  
2.2.2.5  
PIR1 Register  
The PIR1 register contains the interrupt flag bits, as  
shown in Register 2-5.  
Note:  
Interrupt flag bits are set when an interrupt  
condition occurs, regardless of the state of  
its corresponding enable bit or the global  
enable bit, GIE (INTCON<7>). User  
software should ensure the appropriate  
interrupt flag bits are clear prior to  
enabling an interrupt.  
REGISTER 2-5:  
PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)  
R/W-0  
EEIF  
R/W-0  
ADIF  
R/W-0  
U-0  
R/W-0  
CMIF  
R/W-0  
OSFIF  
R/W-0  
R/W-0  
CCP1IF  
TMR2IF  
TMR1IF  
bit 7  
bit 0  
bit 7  
bit 6  
bit 5  
EEIF: EEPROM Write Operation Interrupt Flag bit  
1= The write operation completed (must be cleared in software)  
0= The write operation has not completed or has not been started  
ADIF: A/D Interrupt Flag bit  
1= A/D conversion complete  
0= A/D conversion has not completed or has not been started  
CCP1IF: CCP1 Interrupt Flag bit  
Capture mode:  
1= A TMR1 register capture occurred (must be cleared in software)  
0= No TMR1 register capture occurred  
Compare mode:  
1= A TMR1 register compare match occurred (must be cleared in software)  
0= No TMR1 register compare match occurred  
PWM mode:  
Unused in this mode.  
bit 4  
bit 3  
Unimplemented: Read as ‘0’  
CMIF: Comparator Interrupt Flag bit  
1= Comparator 1 output has changed (must be cleared in software)  
0= Comparator 1 output has not changed  
bit 2  
bit 1  
bit 0  
OSFIF: Oscillator Fail Interrupt Flag bit  
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)  
0= System clock operating  
TMR2IF: Timer 2 to PR2 Match Interrupt Flag bit  
1= Timer 2 to PR2 match occurred (must be cleared in software)  
0= Timer 2 to PR2 match has not occurred  
TMR1IF: Timer 1 Overflow Interrupt Flag bit  
1= Timer 1 register overflowed (must be cleared in software)  
0= Timer 1 has not overflowed  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR  
2004 Microchip Technology Inc.  
Preliminary  
DS41211B-page 15