PIC12F683
TABLE 2-2:
PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOD
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83
81h OPTION_REG GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 12, 83
0000 0000 17, 83
0001 1xxx 11, 83
xxxx xxxx 17, 83
82h PCL
Program Counter’s (PC) Least Significant Byte
(1)
(1)
83h STATUS
84h FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
85h TRISIO
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 83
86h
87h
88h
89h
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
8Ah PCLATH
8Bh INTCON
8Ch PIE1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 17, 83
0000 0000 13, 83
GIE
EEIE
PEIE
ADIE
T0IE
INTE
—
GPIE
CMIE
T0IF
INTF
GPIF
CCP1IE
OSFIE
TMR2IE TMR1IE 000- 0000 14, 83
8Dh
—
Unimplemented
—
—
8Eh PCON
—
—
—
—
ULPWUE SBODEN
—
—
POR
LTS
BOD
SCS
--01 --qq 16, 83
-110 x000 28, 83
---0 0000 23, 83
(2)
8Fh OSCCON
90h OSCTUNE
IRCF2
—
IRCF1
—
IRCF0
TUN4
OSTS
TUN3
HTS
TUN2
TUN1
TUN0
91h
—
Unimplemented
—
—
92h PR2
93h
Timer2 Module Period Register
Unimplemented
1111 1111 45, 83
—
—
—
—
—
—
94h
Unimplemented
(3)
95h WPU
96h IOC
97h
—
—
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0 --11 -111 32, 83
IOC3
IOC0
--00 0000 33, 83
—
—
Unimplemented
Unimplemented
—
—
—
—
98h
99h VRCON
9Ah EEDAT
9Bh EEADR
9Ch EECON1
9Dh EECON2
9Eh ADRESL
9Fh ANSEL
VREN
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 53, 83
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 65, 83
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 65, 83
—
—
—
—
WRERR
EEPROM Control Register 2 (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1
WREN
WR
RD
---- x000 66, 84
---- ---- 66, 84
xxxx xxxx 57, 84
-000 1111 59, 84
—
ANS0
Legend:
— = unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: OSCCON<OSTS> bit reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator.
3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
DS41211B-page 10
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
