MCP3201
6.2
Maintaining Minimum Clock Speed
6.4
Layout Considerations
When the MCP3201 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample cap while the conversion is taking
place. At 85°C (worst case condition), the part will
maintain proper charge on the sample capacitor for at
least 1.2ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2ms (effective clock fre-
quency of 10kHz). Failure to meet this criteria may
induce linearity errors into the conversion outside the
rated specifications. It should be noted that during the
entire conversion cycle, the A/D Converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
When laying out a printed circuit board for use with ana-
log components, care should be taken to reduce noise
wherever possible. A bypass capacitor should always
be used with this device and should be placed as close
as possible to the device pin. A bypass capacitor value
of 1µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possi-
ble from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccu-
rate conversion results may occur. See Figure 4-2. It is
also recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results. This is illustrated in Figure 6-3 where an op
amp is used to drive the analog input of the MCP3201.
This amplifier provides a low impedance source for the
converter input and a low pass filter, which eliminates
unwanted high frequency noise.
VDD
Connection
Device 4
Device 1
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
Device 3
Device 2
VDD
FIGURE 6-4: VDD traces arranged in
a
‘Star’
10µF
configuration in order to reduce errors caused by
current return paths.
4.096V
Reference
1µF
Tant.
0.1µF
0.1µF
ADI
REF198
1µF
VREF
IN+
MCP3201
IN-
C
1
MCP601
R
1
+
-
R
2
VIN
C
2
R
4
R
3
FIGURE 6-3: The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3201.
FilterLab is a trademark of Microchip Technology Inc. in
the U.S.A and other countries. All rights reserved.
DS21290B-page 16
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
