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ENC28J60-I/SO 参数 Datasheet PDF下载

ENC28J60-I/SO图片预览
型号: ENC28J60-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 独立以太网控制器,SPI接口 [Stand-Alone Ethernet Controller with SPI Interface]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路光电二极管数据传输PC局域网以太网时钟
文件页数/大小: 96 页 / 1466 K
品牌: MICROCHIP [ MICROCHIP ]
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ENC28J60  
TABLE 3-2:  
ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED)  
Value  
on  
Reset  
Details  
on  
Page  
Register Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
EPMCSL  
EPMCSH  
Pattern Match Checksum Low Byte (EPMCS<7:0>)  
Pattern Match Checksum High Byte (EPMCS<15:0>)  
Pattern Match Offset Low Byte (EPMO<7:0>)  
0000 0000  
0000 0000  
51  
51  
EPMOL  
0000 0000  
---0 0000  
1010 0001  
0000 0000  
51  
51  
48  
43  
34  
35  
36  
36  
34  
34  
34  
34  
34  
34  
21  
19  
19  
19  
19  
19  
34  
34  
34  
34  
34  
34  
76  
75  
76  
76  
21  
22  
6
EPMOH  
Pattern Match Offset High Byte (EPMO<12:8>)  
ERXFCON  
EPKTCNT  
MACON1  
MACON3  
MACON4  
MABBIPG  
MAIPGL  
UCEN  
ANDOR  
CRCEN  
PMEN  
MPEN  
HTEN  
MCEN  
BCEN  
Ethernet Packet Count  
r
TXPAUS  
PHDREN  
RXPAUS  
HFRMEN  
PASSALL  
FRMLNEN  
r
MARXEN ---0 0000  
PADCFG2  
PADCFG1  
DEFER  
PADCFG0 TXCRCEN  
BPEN NOBKOFF  
FULDPX  
r
0000 0000  
-000 --00  
-000 0000  
-000 0000  
-000 0000  
---- 1111  
--11 0111  
0000 0000  
0000 0110  
---- --00  
---0 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
---- 0000  
---q qqqq  
Back-to-Back Inter-Packet Gap (BBIPG<6:0>)  
Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)  
Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)  
MAIPGH  
MACLCON1  
MACLCON2  
MAMXFLL  
MAMXFLH  
MICMD  
Retransmission Maximum (RETMAX<3:0>)  
Collision Window (COLWIN<5:0>)  
Maximum Frame Length Low Byte (MAMXFL<7:0>)  
Maximum Frame Length High Byte (MAMXFL<15:8>)  
MIISCAN  
MIIRD  
MIREGADR  
MIWRL  
MII Register Address (MIREGADR<4:0>)  
MII Write Data Low Byte (MIWR<7:0>)  
MII Write Data High Byte (MIWR<15:8>)  
MII Read Data Low Byte (MIRD<7:0>)  
MII Read Data High Byte(MIRD<15:8>)  
MAC Address Byte 5 (MAADR<15:8>)  
MAC Address Byte 6 (MAADR<7:0>)  
MIWRH  
MIRDL  
MIRDH  
MAADR5  
MAADR6  
MAADR3  
MAADR4  
MAADR1  
MAADR2  
EBSTSD  
EBSTCON  
EBSTCSL  
EBSTCSH  
MISTAT  
MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3  
MAC Address Byte 4 (MAADR<23:16>)  
MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1  
MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2  
Built-in Self-Test Fill Seed (EBSTSD<7:0>)  
PSV2  
PSV1  
PSV0  
PSEL  
TMSEL1  
TMSEL0  
NVALID  
TME  
BISTST  
BUSY  
Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>)  
Built-in Self-Test Checksum High Byte (EBSTCS<15:8>)  
r
SCAN  
EREVID(2)  
ECOCON(3)  
EFLOCON  
EPAUSL  
Ethernet Revision ID (EREVID<4:0>)  
COCON2  
FULDPXS  
COCON1  
FCEN1  
COCON0 ---- -100  
FCEN0  
---- -000  
0000 0000  
0001 0000  
56  
57  
57  
Pause Timer Value Low Byte (EPAUS<7:0>)  
Pause Timer Value High Byte (EPAUS<15:8>)  
EPAUSH  
Legend:  
Note 1:  
x= unknown, u= unchanged, — = unimplemented, q= value depends on condition, r = reserved, do not modify.  
CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.  
EREVID is a read-only register.  
2:  
3:  
ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets.  
DS39662B-page 14  
Preliminary  
© 2006 Microchip Technology Inc.